1. Field of the Invention
The present invention is related to a Dynamic Random Access Memory (DRAM) and, more particularly, to reliable DRAM timing for connecting memory cell data on a bit line to a data bus.
2. Description of Related Art
In the field of semiconductor memory devices, various technological improvements have been promoted and proposed from the view point of a high speed operation and high integration.
An example was disclosed in Japanese Patent Publication: JP-A-3165398 published on Jul. 17, 1991, which aimed at a high speed memory device by improving a column decoder providing a memory cell array with a column selection signal. Another example was disclosed in the U.S. Pat. No. 4,344,005 issued on Aug. 10, 1982, which devised the method of controlling a column decoder.
However, it is an object of the present invention to provide a semiconductor memory device that can perform at higher speed and with more reliable operation by further improving various memory devices which have been proposed and improved.
It is another object of the present invention to provide a semiconductor memory device-which does not hinder a high integration and not complicate the manufacturing process, which memory device can be realized by a simple design.